As semiconductor memory devices, dynamic RAMs (DRAMs) are well-known products and currently used in a variety of electronic devices. A memory cell which is a key component in a DRAM includes a read and write transistor and a capacitor.
Circuit patterns for DRAMs, like those for other semiconductor integrated circuits, have been miniaturized in accordance with the scaling law, and there was a time when it was considered difficult to achieve a design rule of 100 nm or less. One of the reasons is that in a transistor having a channel length of 100 nm or less, a punch-through current is likely to flow due to a short-channel effect and the transistor becomes incapable of functioning as a switching element, which has been considered to be a problem. In order to prevent a punch-through current, a silicon substrate may be doped with an impurity at high concentration. However, this is not an appropriate solution to the problem because it makes a junction leakage current likely to flow between a source and the substrate or between a drain and the substrate and eventually causes a deterioration of memory retention characteristics.
Against such a problem, a method has been considered for reducing the area occupied by one memory cell and also maintaining an effective channel length so as not to cause a short-channel effect by forming a three-dimensional transistor in the memory cell. One example is a structure in which a U-shaped vertically long groove is formed in a region where a channel portion of a transistor is formed, a gate insulating film is formed along a wall surface in the groove, and a gate electrode is formed so as to fill the groove (see Reference 1).
A transistor having a channel portion of such a structure has a long effective channel length because a current flows between a source region and a drain region via an indirect route across the groove portion. This provides an advantageous effect of reducing the area occupied by a transistor in a memory cell and suppressing a short-channel effect.